Carrier Board Design for Solderable Modules: Footprint, Reflow, and Thermal Considerations

A practical guide to the carrier board for solder-down OSM modules: footprint per IPC-7093A, solder paste process window, reflow profile, MSL deadlines, and thermals.

Key takeaways

• IPC-7093A governs the contact array, not IPC-7351. An LGA is explicitly listed there as a bottom-termination component. The standard provides chapters on solder mask design, via arrays, and fatigue life that are applicable to an OSM array.
• OSM is not a fine-pitch BGA. Size-S has a 1.25 mm pitch and 0.80 mm pads. At a 100 µm stencil thickness, that yields an aspect ratio of 8.0 and an area ratio of 2.0 — both far above the minimums of 1.5 and 0.66.
• The cycle budget is the hardest limit. Components classified per J-STD-020 survive three reflow cycles. F&S permits a total of two for its OSM module. Anyone populating both sides and planning for rework has no budget left.
• Two manufacturers in the same size class specify peak temperatures 10 K apart — for two different soldering processes, and neither says how to convert between them: Kontron 250 °C in convection reflow, F&S 240 °C in vapor phase, Toradex nothing at all as of June 2026. After the dry pack is opened, MSL 3 leaves exactly 168 hours.
• The thermal resistance from the datasheet does not apply to your board. ROHM says so verbatim, and so does NXP. None of the three module manufacturers examined specifies a copper area, a via pattern, a stackup, or a θJA for the carrier board.

A solder-down system-on-module forgives no second attempt. Where a plug-in SoM connector allows the module to be swapped, measured, and returned, an OSM module is reflow-soldered once — and then it's fixed in place. That shifts responsibility: everything the connector used to absorb on a plug-in module has to be handled by the carrier board on a solder-down one. Footprint, paste volume, temperature profile, moisture management, and thermal path are no longer manufacturing details but design decisions.

And that is exactly where vendor documentation is loudest in its silence. In the datasheet for its i.MX 93 OSM module, Toradex as of June 2026 lists four sections that would be load-bearing for carrier design under the same word: power consumption "TBA," mechanical drawing "TBA," thermal specification "TBA," soldering and assembly "TBA" (OSM iMX93 Datasheet, Rev. 0.4, Toradex, accessed July 27, 2026).

This guide walks the whole chain through in one piece: from the footprint through paste and reflow to moisture, thermals, and solder joint life. It draws exclusively on publicly available documents — standards from IPC and JEDEC, semiconductor app notes from NXP, ST, and ROHM, plus the implementation documentation from three OSM manufacturers. Where a figure could not be substantiated, the text says so instead of offering an estimate.

The Technologies and expertise page summarizes which SoC platforms and interfaces Teleconnect uses in customer projects.

Contents: What a solder-down module changes · Footprint · Paste and stencil · Reflow · Cycle budget · Thermals · Solder joint life · Documentation gaps · Design review checklist · FAQ · Methodology

What a solder-down module changes on the carrier board

Three things disappear, and each of them used to be a safety net: the connector as a mechanical decoupler, the ability to swap the module, and the clean division of responsibility at the mating interface. What remains is a solder connection that is simultaneously the electrical contact, the mechanical attachment, and the only thermal path.

SGET's OSM standard (Open Standard Module) defines four size classes for this purpose. Size-S is the one commonly used for the i.MX 91 and i.MX 93:

Dimensions and contact counts per SGET, Open Standard Module (accessed July 27, 2026). The current status is OSM Specification 1.2 together with Design Guide 1.1, published on November 11, 2024 (SGET announcement).

For the layout, though, what matters is not the size class but the geometry of the contact array — and that can be determined precisely from the manufacturers' drawings. The dimensional drawings from F&S, Toradex, and Kontron all show the same grid for Size-S: a matrix of 23 rows (A through AC) and 23 columns with a 1.25 mm pitch, 0.80 mm pad diameter, and 0.85 mm from the module edge to the outer pad edge. The cross-check works out: 23 pad rows span 22 pitches, so 22 × 1.25 mm = 27.50 mm center to center, plus 0.80 mm once for the two outer pad halves and 0.85 mm twice for the edge clearance — for exactly 30.00 mm in total, the nominal outer dimension (F&S Application Note OSM01, V. 006/04.2026, F&S Elektronik Systeme, accessed July 27, 2026).

That's the first piece of good news in this article: a 1.25 mm pitch with 0.80 mm pads is relaxed from a process standpoint. An OSM contact array is not a fine-pitch BGA. Anyone expecting the manufacturing risks of a 0.4 mm pitch is budgeting for effort that doesn't arise here.

Two quirks matter more than the pitch. First: of the 529 grid positions, only 332 are populated, and they form a ring with a hollow center. Second: this means OSM Size-S has no central thermal pad, unlike QFN and other bottom-termination components. Both have consequences for the thermal path, which the thermals section returns to.

Not every solder-down module is an OSM module. Proprietary LGA modules in the same performance class exist with different edge lengths and contact counts. They are not technically inferior, but they tie the design to one vendor, and the footprint isn't transferable. How far the documentation reaches for the i.MX 91 and i.MX 93 modules available on the market is worth its own analysis; that will appear as a separate article.

Footprint: which standard applies — and which doesn't

IPC-7093A is the relevant one, not IPC-7351. IPC-7351B is a generic land pattern ruleset for SMD components. For components with planar terminations underneath the body, IPC-7093A "Design and Assembly Process Implementation for Bottom Termination Components (BTCs)," October 2020, takes precedence — and there the land grid array is explicitly named as a BTC example (IPC, accessed July 27, 2026).

That's more than a formality. IPC-7093A contains exactly the chapters a carrier designer needs: §6.8 Solder Mask Design, §6.10 Thermal Via Types including via count and arrangement, §6.11.5 Via-in-Pad Plated-Over, §6.13/6.14 Stencil Design and Aperture Reductions, and §8 on fatigue life. Search IPC-7351 and you won't find these chapters.

NSMD or SMD: the pad decision

For LGA pads, NSMD (non-solder-mask-defined) is the baseline case. ST puts it this way in its app note on LGA packages: "It is recommended to use a non solder mask defined (NSMD) pads … with opening slightly larger than the land geometry." As a figure, ST names a minimum mask opening enlargement of 0.050 mm to account for solder mask registration tolerance, and a 1:1 ratio between package pad and PCB pad (AN5886 Rev. 2, May 2024, §2.1, STMicroelectronics, accessed July 27, 2026).

The reason is a manufacturing one: copper etching holds tolerance better than the solder mask. With NSMD, the solder also wets the pad flank, which ST describes as "better solder joint reliability." The price appears in the same source: NSMD pads "tend to peel off during multiple reworks and reflows." SMD pads are mechanically stronger because the mask overlaps them, and they need less routing space.

Important when transferring this to OSM: ST only flips the recommendation to SMD with trench openings at pitches of 0.4 mm and below. At 1.25 mm you're nowhere near that, so NSMD remains the baseline. Also note that AN5886 addresses LGA packages with pitches from 0.35 to 1.0 mm. For an OSM module, the app note is a well-founded analogy, not a directly binding requirement.

There's a second argument for NSMD that comes from an entirely different direction. The qualification test vehicle per IPC-9701 is specified with NSMD pads and a board thickness of 93 mil (about 2.36 mm) (NASA NEPP, Ghaffarian, JPL/Caltech, slide 5, nepp.nasa.gov, accessed July 27, 2026). Use SMD pads and you leave the boundary conditions under which published solder joint reliability cycle counts were determined. Those numbers then no longer apply directly.

Vias under the module

Open vias under the contact array are a short-circuit risk. Kontron states this as a requirement: "There should be no open vias under the SoM on the baseboard, as this poses a risk of short circuits. Therefore, the vias under the SoM should be plugged." (OSM-S i.MX93 DC SoM-Module User Guide, Rev. 1.0, May 14, 2025, §11, Kontron Electronics, accessed July 27, 2026).

"Plugged" is a defined term here. IPC-4761 "Design Guide for Protection of Printed Board Via Structures" distinguishes seven via protection types, from tented (type I) through plugged (type III) and filled (type V) to filled and capped (type VII, commonly called VIPPO) (IPC, accessed July 27, 2026). The types differ considerably in manufacturing effort and cost. This decision belongs in the manufacturing discussion, not in the final layout phase — decide it too late and you pay for a new stackup revision. Footprint, stackup, and manufacturing coordination belong together; at Teleconnect that falls under PCB design.

Paste and stencil: the process window

A fully documented paste window exists for OSM Size-S — but only from one of the three manufacturers examined. F&S publishes it as a closed parameter table:

Source: F&S Application Note OSM01, Table 22, V. 006/04.2026. The table applies to both the LGA and the FTGA variant of the module.

Both ratios can be recalculated, and it's worth doing, because they show how much margin the process holds. The aspect ratio is aperture width divided by stencil thickness: 0.80 mm / 0.100 mm = 8.0. The area ratio is the aperture area divided by the aperture wall area, so for a round opening (π/4 · 0.80²) / (π · 0.80 · 0.100) = 0.503 / 0.251 = 2.0. For comparison: ST requires an area ratio above 0.66 for LGA packages with laser-cut stencils and an aspect ratio above 1.5 (AN5886 §3.2). An OSM contact array sits at three times and five times those minimums respectively.

The convergence on stencil thickness is notable: ST names 100 µm for a 0.4 mm pitch, F&S names 100 µm for a 1.25 mm pitch. The same thickness at three times the pitch means the paste quantity per contact is far less critical on OSM.

Three further values belong in the manufacturing specification:

• Standoff after reflow: about 75 µm. F&S identifies this as an internal validation, determined with a 100 µm stencil, SAC305 (Type 4 or finer), and vapor phase soldering (AN OSM01 §2.1.2, footnote). The value matters because standoff height influences fatigue life.
• Placement accuracy: ±50 µm or better. ST names this as a pick-and-place requirement for LGA packages with high contact density (AN5886 §3.5). At a 1.25 mm pitch that's comfortably achievable; per F&S, however, an LGA's self-centering is only mediocre, which is why placement has to be more precise than for a ball BGA.
• No cut-out, no spacer. F&S modules are single-sided; the carrier needs neither a cutout nor a standoff. A small production-related overhang at the corners has to be allowed for — nominally 30.0 mm, 30.5 mm with overhang (AN OSM01 §2.1.1).

Important for process planning: on the LGA variant, the entire solder volume is determined by the carrier stencil. There is no pre-tinned bump on the module contributing anything. On the optional FTGA variant (fused tin grid array) it's the reverse — there, module and carrier solder add up, bridging risk rises, and F&S recommends an aperture reduction. Switch between the variants and you have to adapt the stencil.

Reflow: 240 °C, 250 °C, or TBA?

The temperature profile is where the sources fall apart. First the normative framework. The classification profile per IPC/JEDEC J-STD-020 is fully documented via a freely available primary-manufacturer source (Texas Instruments, MSL Ratings and Reflow Profiles, SPRABY1A, February 2015, revised December 2018, Texas Instruments, accessed July 27, 2026):

• Soak from 150 °C to 200 °C, duration 60 to 120 s
• Liquidus at 217 °C (lead-free), time above it 60 to 150 s
• Ramp-up to peak 3 °C/s maximum, ramp-down 6 °C/s maximum
• Time within 5 K below peak 30 s maximum
• From 25 °C to peak 8 minutes maximum

The permitted peak temperature depends on the component's thickness and volume:

And here some honesty is due: J-STD-020 classifies non-hermetic, encapsulated components. An OSM module is not a molded package but a populated circuit board with its own component mix, its own warpage, and its own moisture history. The table by thickness and volume is therefore an analogy for a module, not a directly binding requirement. It tells you the order of magnitude the limit sits at — not what your module will withstand.

Two profiles, two processes, 10 K apart

What the module will withstand ought to come from the module manufacturer. Two of three provide it, with different results:

Kontron gives a complete convection profile, and its framework matches the classification profile exactly: soak 150 to 200 °C in 60 to 120 s, liquidus 217 °C, ramp-up 3 °C/s maximum, ramp-down 6 °C/s maximum, 8 minutes from 25 °C to peak. The peak sits at 250 °C with a 20 s dwell, and time above liquidus at 60 to 80 s (User Guide Rev. 1.0, §11, Table 15).

F&S gives a vapor phase profile only, with a peak of 240 °C and 15 s typical to 30 s maximum. Along with three boundary conditions, verbatim: "The profile is only valid for Vapor Phase-Soldering. Reflow may require higher temperatures. 260 °C must not be exceeded." and "The total time above 60 °C must not exceed 600 s." (AN OSM01 §3.3.4).

That leaves two specifications for the same SGET size class sitting 10 K apart, with the Kontron figure exceeding the derived classification temperature by 5 K. Both are explainable: vapor phase soldering and convection reflow are different processes with different heat transfer, and a module is not a classified package. But that is precisely the point. The profiles are not interchangeable, and none of the manufacturers says how to convert between them. Process an F&S module in a convection oven and you are working outside the only specification the manufacturer provides — with an explicit note that it will have to get hotter there and that 260 °C must never be exceeded.

As a third, independent data point: for LGA packages generally, ST specifies a ramp-to-spike profile with a 240 ± 5 °C peak, 55 ± 10 s above 220 °C, and a cooling gradient of −3 ± 2 °C/s (AN5886 §3.6, Table 3). The 240 °C order of magnitude is thus supported by two independent sources.

Practical consequence: request the profile for your process in writing before you design the module in — and have them tell you which soldering process it applies to. With a module that has no documented profile, you aren't negotiating over a number but over who carries the process risk.

The cycle budget: two solder passes, not three

This is the calculation none of the vendor documents performs. Components classified per J-STD-020 survive three reflow cycles (TI SPRABY1A §5). For the OSM module, F&S explicitly permits fewer: "Only 2 soldering cycles are permitted in total." (AN OSM01 §3.3.4), and that on the precondition of a "Dry OSM module (MSL 3)."

Two cycles is tight. A double-sided carrier board already consumes two passes if the module sits on the second side or goes through the first pass with everything else. That leaves nothing for a rework operation. Kontron draws the obvious conclusion and states it as a recommendation: "To minimize stress for the components, it is strongly recommended to solder the SoM during the last reflow cycle of the carrier board manufacturing process." (User Guide §11).

Two design rules follow, and they have to precede the layout, not follow it:

1. The module goes into the last reflow pass. Meaning: on the side populated last, and in an assembly sequence that triggers no further trip through the oven.
2. A rework budget has to be confirmed by the manufacturer. IPC-7093A covers rework for bottom-termination components in §7.12, including hot air rework. Whether the module survives such an operation is stated by none of the three documents.

The moisture clock starts when the bag is opened

The second hard deadline is floor life. Both F&S OSM variants are classified MSL 3. Per J-STD-033, that means a processing window of 168 hours at 30 °C and 60 % relative humidity (TI SPRABY1A Table 1, per IPC/JEDEC J-STD-033):

168 hours is seven days. That's the real deadline between opening the dry pack and reflow — not between goods receipt and production start. Two details tighten it:

• Floor life has to be considered again after the first reflow as well. TI puts it as "For IC products with MSL Rating 2 and lower, the floor life needs to also be considered after a first reflow." Reading it this way is our own interpretation: what's meant is robustness, not the numeral, since MSL 1 has unlimited floor life at 30 °C and 85 % relative humidity and wouldn't be affected by the rule. An MSL 3 module is thus included. So running two cycles consumes the clock not once but twice.
• Moisture doesn't only affect the module. IPC-7093A addresses moisture absorption by the circuit board in §5.3. A carrier that goes into the oven after storage without pretreatment brings its own water along.

This article deliberately gives no figures for baking conditions. The values circulating online ("125 °C for 24 to 192 hours depending on body thickness") could not be traced to a retrievable primary source. All that can be substantiated is that tape-and-reel material must not be baked above 40 °C and that J-STD-033 grades the times by body thickness. Ask the manufacturer for the conditions rather than adopting a table from a forum.

Thermals: why the datasheet is not your board

The thermal resistance from a semiconductor datasheet is not a design basis for your carrier board. That isn't an interpretation; it's what the sources say. ROHM puts it this way in an app note on the topic: "The purpose of measuring θJA is only to compare the thermal performance of one package with another in a standardized environment. θJA is neither intended nor able to predict package performance in application-specific environments." In the summary table of the same app note, the row "Junction temperature estimation" simply reads, for θJA: "Not possible" (ROHM 65AN114E Rev. 001, February 2023, fscdn.rohm.com, accessed July 27, 2026).

The reason lies in the measurement condition. θJA — often written RθJA in semiconductor datasheets, the same junction-to-ambient parameter — is defined in JESD51-1 and JESD51-2A and is determined on standardized test boards per JESD51-3, -5, and -7, under free convection. The JEDEC test board measures 114.3 × 76.2 mm and has four layers. How much the copper area alone shifts the value is shown by the same source:

The datasheet value sits at the right end of the curve — the most favorable case. A real carrier with a limited ground plane sits to the left of it. What is practically usable instead is ΨJT, the junction-to-package-top parameter: it stays nearly constant across the entire area range, because SMD components dissipate most of their heat downward into the board, so the upward path carries almost no power. With ΨJT and a measured surface temperature, junction temperature can be estimated; with θJA it cannot.

With a module, a whole circuit board sits in between

For the i.MX 93 itself, the values are well documented. In the industrial datasheet, NXP names an RθJA of 21.7 °C/W and a ΨJT of 0.1 °C/W for the 14 × 14 mm FCPBGA, and 22.5 and 23.5 °C/W for the smaller variants (IMX93IEC Rev. 7, February 12, 2026, Tables 10 through 12, NXP, accessed July 27, 2026). Junction temperature is specified as −40 to +105 °C for the industrial variant and up to +125 °C for extended industrial.

These numbers are precise — and still not usable for a carrier board with a solder-down module. The footnote to all three tables gives the condition: "Thermal test board meets JEDEC specification for this package (JESD51-9). Test board has 40 vias under die shadow mapped according to BGA layout under die. Each via is 0.2 mm in diameter and connects top layer with the first buried plane layer." And the next footnote repeats the warning ROHM already issues: "It is not meant to predict the performance of a package in an application-specific environment."

With an OSM module, an entire additional circuit board — the module's own — sits between that via cluster and your carrier. The via cluster under the die is already part of the module and not yours to shape. Your carrier sees only the contact array. The 21.7 °C/W therefore cannot be applied to this stack without an analysis of your own, not even as a rough upper or lower bound: the sources say the value isn't intended for prediction, and they say nothing about bounds. What's missing is telling, too: RθJB, junction-to-board resistance, does not appear in the three tables. That would be the value closest to a module-level analysis.

What NXP tells the board designer

The hardware design guide for the i.MX 93 contains statements that hold physically for a module-plus-carrier system too, even though the numbers were determined on a directly soldered SoC (IMX93HDG Rev. 1, April 13, 2023, chapter 6, NXP, accessed July 27, 2026):

• "Typically, more than 80 % of the heat generated by a high-power component is dissipated through the system board, when no other thermal solution is implemented." The board is the primary heat sink, not an accessory.
• An NXP sensitivity simulation found that halving the board's x-y dimensions increases package thermal resistance by 44 to 65 %. Building smaller costs temperature budget, and disproportionately so.
• Placing the device off-center on the board raises junction temperature by roughly 8 to 10 %, due to uneven heat spreading.
• The base material's CTE should be as close as possible to that of copper, which is around 17 ppm/°C. Otherwise the plated through-hole elongates on heating and cracks.
• For the stackup, NXP recommends at least six layers, or at least four for the small 9 × 9 mm variant.

The last recommendation is interesting because it partly falls away on an OSM carrier: the reason for six layers is DDR routing and power delivery right at the SoC's ball array. On a solder-down module, both of those sit on the module. It does not follow, however, that an OSM carrier can get by with fewer layers — that conclusion can't be drawn from the document, and the thermal path argues against it.

The missing thermal pad

Here the BTC literature runs into a gap. IPC-7093A addresses the thermal path of bottom-termination components in §6.10 and §6.11 entirely by way of a central thermal pad: via types, via count and arrangement, orthogonal and hexagonal arrays, via-in-pad, plus parameter tables for every thermal pad variant. Figure 6-24 even quantifies the average thermal resistance of a via array versus via density.

An OSM Size-S array has no central pad. Heat has to leave via the contact ring, which means via the ground and supply contacts. Their number is the actual thermal path. At F&S, GND sits on 58 of the 332 contacts, and the 5 V main supply VCC_IN_5V on five contacts (Y8, Y9, Y10, Y11, Y17; counted from the pinout table in AN OSM01). Toradex describes the same principle qualitatively: "The distribution of supply rails across multiple OSM pads improves current-carrying capability, reduces voltage drop, and enhances thermal performance."

For the layout, one clear priority follows: every ground contact under the module belongs connected to a continuous ground plane over a large area, not through a thin stub trace. NXP states the same goal for the SoC case — minimize resistance between device and board by using all ground pads. None of the sources, however, yields a via pattern with numbers. The only substantiated via count in all of the NXP material is the test board cluster from the datasheet footnote, and that is a measurement condition, not a recommendation.

On the cooling side, exactly one vendor-supplied concept exists: F&S offers the MHS.OSM.1, a heat spreader consisting of a spreader plate, thermal interface material, and four M2.5 × 6 mm screws per DIN 965. Kontron warns about the hot surface in the corresponding section and writes: "Please do not operate the OSM-S i.MX93 DC without sufficient cooling system." No number appears in that section.

Solder joint life

On a solder-down module, the solder connection is also the mechanical attachment, and it works against a CTE mismatch. Module and carrier expand differently under temperature cycling; the difference ends up in the solder joint. IPC-7093A documents this for BTCs in §8 and shows a solder crack from CTE mismatch after 1,000 cycles in Figure 8-1.

Four design parameters influence fatigue life per those same chapters, and one of them is counterintuitive:

As countermeasures, the standard devotes its own chapters to reinforcing the solder joint with corner bond, underfill, and adhesives (§8.2.6 and §7.3.6). That isn't a design parameter but an additional measure for cases where temperature cycling or vibration is expected.

A note on how much weight this table carries: what's verified are the titles and statements of the figures, not the plotted curve values. This article therefore names no specific cycle counts or Weibull parameters from those images — with the exception of the 1,000 cycles named explicitly in the title and the 30 percent limit.

On voiding, it pays to look at both sources: IPC-7093A names below 30 % for the thermal pad, while ST recommends "a 25 % maximum voids criteria" for LGA solder joints generally and notes at the same time that there is currently no specific standard for post-reflow voids (AN5886 §4). If you're writing a limit into the manufacturing specification, take the stricter one and provide for X-ray inspection as a spot check.

What qualification data actually says

Cycle counts from reliability studies mean something only together with their boundary conditions. The conditions per IPC-9701 are fully documented via a tier-1 source (NASA NEPP, Ghaffarian, JPL/Caltech, slide 6, reproduced as "Table 1 Temperature cycling requirements specified in Table 4.1 of IPC 9701"):

The standard defines five temperature cycles:

And across from those, five levels for the cycle count:

The two tables only connect through the preferred pairings: TC1 is paired with NTC-E at 6,000 cycles, and TC2 through TC4 with NTC-C at 1,000 cycles. For TC5, the reproduced table names no preferred level. Dwell time is 10 minutes at each end. The test runs at minimum until a cumulative failure rate of 50 %, preferably until the characteristic life of 63.2 %; it ends at the latest when the NTC level is reached. The test vehicle is subject to the same boundary conditions already named in the footprint section — NSMD pads and 93 mil board thickness — plus continuous monitoring; manual measurement is explicitly not permitted.

That gives you a touchstone for supplier claims. A statement like "passed 1,000 cycles" can't be interpreted without the TC condition, dwell time, and failure criterion. One thousand cycles from 0 to 100 °C is a different load than 1,000 cycles from −40 to 125 °C.

Class 2 or Class 3: a design decision, not a formality

IPC-7093A defines three product classes in §1.2, and the choice feeds back into the parameters above. Class 1 "General Electronic Products" essentially requires the finished assembly to function. Class 2 "Dedicated Service Electronic Products" requires continued performance and extended life, where uninterrupted service is desired but not critical and the end-use environment would typically not cause failures. Class 3 "High Performance/Harsh Environment" applies where continued high performance is critical and downtime cannot be tolerated.

The decision should be made before layout, because it determines land size, board thickness, the voiding limit, the question of corner bond or underfill, and the scope of testing. Leave it open and you decide it implicitly: manufacturing then works to its own default requirements, without the class being documented anywhere. For an industrial device with a ten-year field life and wide temperature swings, that's a risk avoidable with one line in the requirements specification. We support this classification and the qualification of a second supplier as part of our hardware development work.

What the module manufacturers don't document

Across three manufacturers in the same size class, not one documents carrier thermals. The following matrix is the result of evaluating the three current implementation documents:

The bottom half of the table is the real story. Copper area, via pattern, stackup, and thermal resistance for the carrier board are specified by no manufacturer — that is, precisely the thermal path that on a solder-down module, with no socket and no central thermal pad, runs exclusively through the board.

Toradex's chain of references is instructive. Section 3.1 "Carrier Board Design Considerations" names four topics correctly: "Pad geometry and solder mask definition · Placement accuracy and coplanarity · Reflow soldering profile · Keep-out areas and component clearance." Then it says: "The carrier board must implement the OSM Size-S land pattern as defined by the Open Standard Module specification" and "For more information, refer to the Section 9." Section 9.2.2 is the thermal specification — and there it says "TBA." The reference leads nowhere, and the referenced specification is free from SGET but only available after registration — which is why this article did not evaluate its contents (details in the methodology section).

One final detail with signal value: Toradex ships evaluation samples pre-soldered onto an adapter board that routes the OSM pad matrix to two Samtec 400-pin connectors, "enabling immediate evaluation without additional hardware." So for evaluation, the manufacturer avoids the soldering itself. For production, you carry it.

Carrier board design review checklist

This list consolidates the substantiated requirements from the sections above. It's no substitute for a manufacturing review, but it makes visible which points have to be answered before design release.

Footprint and stackup

• Land pattern designed per IPC-7093A, not IPC-7351
• NSMD pads, mask opening at least 0.050 mm larger than the pad, 1:1 ratio to the module pad
• Pitch and pad diameter checked against the dimensional drawing of the specific module, not against a generic OSM figure
• Vias under the module closed; IPC-4761 type selected and agreed with the PCB fabricator
• Module corner overhang accounted for in the keep-out
• All ground contacts connected to a continuous ground plane over a large area

Paste and placement

• Stencil thickness, aperture diameter, aspect and area ratio calculated against the manufacturer's requirement
• Paste type and alloy specified (SAC305, Type 4 or finer), no-clean flux
• SPI target volume and height carried into the manufacturing specification
• Pick-and-place tolerance at least ±50 µm
• For FTGA modules: aperture reduction provided for, shorter shelf life planned in

Reflow and process sequence

• Profile for the process actually used confirmed by the manufacturer (vapor phase and convection are not interchangeable)
• Absolute temperature ceiling and maximum time above 60 °C documented
• Module in the last reflow pass; assembly sequence specified accordingly
• Cycle budget drawn up: number of oven passes plus planned rework calculated against the permitted cycle count
• Rework procedure for the module clarified in writing

Moisture management

• Module's MSL level known and floor life recorded in the production plan
• Baking conditions obtained from the manufacturer, not taken from secondary sources
• Floor life reconsidered after the first reflow
• Moisture absorption by the carrier itself accounted for

Thermal path

• No θJA from a semiconductor datasheet used as a design basis
• Module power dissipation under real load requested, not derived from the SoC datasheet
• ΨJT or RθJB requested for the module; if unavailable, thermal measurement on the assembly planned
• Ground and copper area designed as the primary thermal path; board area not reduced without a thermal analysis
• Module not placed in a corner of the board
• Cooling concept selected: manufacturer's heat spreader, a custom heat sink, or forced convection
• Thermal simulation or measurement on the real assembly planned in

Reliability

• Product class per IPC-7093A selected and documented
• Voiding limit in the manufacturing specification, X-ray sampling agreed
• Base material CTE checked against the requirement
• Corner bond or underfill evaluated where temperature cycling or vibration is expected
• Supplier cycle-count claims accepted only with TC condition, dwell time, and failure criterion

Questions for the module supplier

These six questions follow directly from the gaps in the documentation matrix:

1. Which soldering process does your profile apply to, and what absolute ceiling applies?
2. How many soldering cycles are permitted in total, and does that include rework?
3. What MSL level does the module have, and what are the baking conditions?
4. What power dissipation occurs under our load profile, at what temperature do you throttle, and can you give a ΨJT or RθJB for the module?
5. What copper area and via pattern do you assume in the carrier?
6. Is there a reference carrier design or a schematic review offering?

On the third and fifth questions, it pays to insist on a written answer. If you'd rather not handle the carrier design or the process coordination alone: talk to us about carrier board design.

Frequently asked questions

Does an OSM carrier board need six layers?

That can't be derived from the vendor documents. NXP recommends at least six layers for a board with a directly soldered i.MX 93, citing DDR routing and power delivery at the ball array. On a solder-down module both of those sit on the module, so the chain of reasoning partly falls away. But it doesn't follow that fewer layers suffice: with OSM, the thermal path runs exclusively through the carrier, and here ground plane is cooling area. None of the three module manufacturers gives a stackup recommendation.

Is an OSM contact array harder to solder than a BGA?

No, from a process standpoint it's more relaxed. The 1.25 mm pitch and 0.80 mm pad diameter give an aspect ratio of 8.0 and an area ratio of 2.0 at a 100 µm stencil thickness, while the minimum requirements are 1.5 and 0.66. Something else is more demanding: an LGA self-centers less well during reflow than a ball BGA, the solder volume on the LGA variant comes entirely from the carrier stencil, and rework is essentially not provided for.

How many reflow cycles can a solder-down module take?

The manufacturer has to say, and the figures differ from the standard. Components classified per J-STD-020 survive three cycles. F&S permits a total of two for its OSM module. Kontron names no number but recommends soldering the module in the last reflow cycle. Toradex documents nothing on this as of June 2026. Plan the budget before layout, because double-sided assembly and rework are both paid for out of it.

Can I use the θJA value from the SoC datasheet for thermal calculations?

No. Both ROHM and NXP explicitly rule that out in their documents: the value serves to compare two packages in a standardized environment and is not intended to predict behavior in a specific application. With a module there's the added fact that another circuit board sits between the measurement setup and your carrier. What is usable is ΨJT together with a measured package surface temperature, or a thermal simulation of the real assembly.

Why do thinner boards improve solder joint life?

IPC-7093A shows this relationship in Figure 8-2 as a Weibull plot: thinner circuit boards yield higher fatigue life. The effect is counterintuitive, because thinner boards are mechanically less stiff — but that is exactly what reduces the strain load in the solder joint during temperature cycling. This explanation is a physical interpretation, not a statement of the standard. The specific cycle counts from the figure aren't reproduced here either, because only the figure's title and directional statement are verified, not the curve values.

What is the difference between the LGA and the FTGA variant?

LGA contacts are ENIG-plated and flat; all the solder comes from the carrier stencil. FTGA contacts (fused tin grid array) are pre-tinned with SAC305, so module and carrier solder add up. FTGA tolerates more warpage and coplanarity deviation and self-centers somewhat better, but carries a higher bridging risk, requires an aperture reduction, and is more prone to oxidation, hence has a shorter shelf life. Both variants are classified MSL 3 at F&S.

Conclusion

A solder-down module shifts risk from the connector into your manufacturing process. The good news is that the process itself is manageable: a 1.25 mm pitch with 0.80 mm pads is uncritical, the paste window is fully documented by one manufacturer, and the chain of standards from IPC-7093A through J-STD-020 and J-STD-033 to IPC-9701 is solid.

The bad news is in the bottom half of the documentation matrix. On the thermal path — that is, on what runs exclusively through your board on a solder-down module with no socket and no central thermal pad — not one of the three manufacturers examined releases a number. The thermal resistance from the SoC datasheet doesn't help, because it was measured under conditions your assembly doesn't reproduce. Leave that gap open and you're relying on a value explicitly not intended for prediction.

Three things are therefore worth doing before design release: draw up the cycle budget, get the reflow profile for your own process confirmed in writing, and ask for power dissipation under the real load profile. Use the question list from the "Questions for the module supplier" section as an inquiry template — six questions, asked in writing, separate the vendors faster than any datasheet comparison.

You'll find more technical articles on the Teleconnect blog.

Methodology and sources

This article is based exclusively on publicly available documents reviewed in July 2026. Ten standards and standard excerpts were evaluated (IPC-7093A, IPC-7351B, IPC-4761, IPC-9701 and -9701B, IPC-2152, IPC/JEDEC J-STD-020E and -020F, J-STD-033, J-STD-001, IPC-A-610, the JESD51 series), along with six semiconductor and reliability documents (Texas Instruments SPRABY1A, ROHM 65AN114E, STMicroelectronics AN5886 Rev. 2, NXP IMX93HDG, NXP IMX93IEC, NASA NEPP / JPL) and the current implementation documentation from three OSM manufacturers (F&S AN OSM01, Kontron OSM-S i.MX93 DC User Guide, Toradex OSM iMX93 Datasheet).

Five limitations matter when weighing the statements:

1. Paywall. The full texts of IPC-7093A, IPC-7351B, IPC-9701B, IPC-2152, J-STD-020, and J-STD-033 are paid documents. What's substantiated from them are the freely available tables of contents and excerpts, plus numeric values reproduced through freely accessible primary-manufacturer documents. The table values for classification temperature and floor life therefore come from TI SPRABY1A, which cites J-STD-020 and J-STD-033 as its source.
2. Login. OSM Specification 1.2 and Design Guide 1.1 are accessible from SGET only after registration. Their contents were not evaluated.
3. Values read off charts. The θJA value pairs from the ROHM curve were read off the diagram, with an accuracy of about ±3 °C/W.
4. Our own derivations are marked as such in the text: the volume class of an OSM Size-S per J-STD-020, the cross-check of the outer dimension from pitch, pad diameter, and edge clearance, the recalculation of aspect and area ratio, the count of ground and supply contacts from the pinout table, the reading of "MSL Rating 2 and lower," and the physical interpretation regarding board thickness.
5. Citation links. The NXP documents IMX93HDG and IMX93IEC are cited via the official documentation portal docs.nxp.com, because the direct PDF endpoints respond inconsistently to automated requests. The PDF versions were reviewed for content (IMX93HDG Rev. 1, IMX93IEC Rev. 7). st.com and fs-net.de also don't respond reliably to automated requests; both documents were reviewed in full text on July 27, 2026, before being cited.

Not included in this article are figures that could only be substantiated through secondary sources: the baking times from J-STD-033, coplanarity and warpage limits in micrometers, specific current-carrying values from IPC-2152, and the current capacity per OSM contact, which could not be found in any freely accessible source. Where a manufacturer doesn't publish a figure, this article says "not documented" rather than offering an estimate.